Electronic lock arrangement having parallel coded input

ABSTRACT

An electronic lock arrangement is disclosed, the arrangement comprising a plurality of consecutively disposed code step circuits. Each circuit, when actuated by an input code pulse train, generates a parallel output, which outputs define a lock release output signal when the input code pulse train is received in proper predetermined order.

I United States Patent 051 3,656,114 Hesselgren [451 Apr. 11, 1972 1ELECTRONIC LOCK ARRANGEMENT 3,080,547 3/1963 Cooper ..340/164 HAVINGPARALLEL CODED INPUT 3,327,290 6/1967 Eglish ..340/164 x 2,855,58810/1958 Allen ..340/164 UX [72] i f gg' Bmnsvagen 3,046,526 7/1962Scantlin ..340/164 3,100,389 8/1963 Noregaard ..340/164 UX [22] Filed:May 1, 1969 3,175,191 3/1965 Cohn........,. .....340/l64 [211 App] No820 921 3,380,024 4/1968 Watkinson ..340/164 Primary Examiner-Harold I.Pitts [30] Foreign Application Priority Data Attorney-Holman & Stem M7,1968 S d ..611 68 ay we 3/ 57 ABSTRACT [52] Cl "340/164! 340/167340/274 An electronic lock arrangement is disclosed, the arrangement[5]] lat. Cl. ..H04g 3/02 comprising a m m of consecutively disposedcode t Fleld ofSearch cuits Each circuit when actuated an i p d pulsetrain, generates a parallel output, which outputs define a lock [56]Reerences C'ted release output signal when the input code pulse train isUNITED STATES PATENTS received in proper predetermined order.

3,024,452 3/1962 Leonard ..340/274 3 Claims, 3Drawing Figures w 76 0 o oo (T v1 v2 v3 l'/ v4 evz ova ev4 L3 l l 1 1 l r 1 7 1 Go Gb Gc LormSHEET 1 BF 3 umu INVENTOR 776-, flan-a (new ATTORNEYS W I a PATENTEDAPR1 1 I972 oer ELECTRONIC LOCK ARRANGEMENT HAVING PARALLEL CODED INPUTDESCRIPTION OF INVENTION have all been rather complicated and in lack ofthe desired security. One type uses electro-mechanical step selectorswith step-wise feeding in accordance with a predetermined set code, butthis means the presence of a number of movable parts, the operations ofwhich can be acoustically localized, thus simplifying a forcing thereof.They are also rather lumbering and not very well suited for automizedmanufacturing.

, Relay chains with mechanical relays have also been suggested for thesame or similar purposes, where the relays are to be actuated in acertain order for obtaining the desired result. A change of code settingwill in this'case be rather complicated as will be a neutralizing of thewhole arrangement in connection with wrong handling.

Still another type of electronic code locks is previously known inprinciple including a number of code steps, which are serially actuatedone after the other according to a predetermined code and where the laststep when activated generates the control voltage which actuates thelock circuit and releases the lock.

The invention will now be more closely described in connection with theaccompanying drawings, which illustrate a practical embodiment of theinvention and where 1 FIG. 1 illustrates the principle design of theinvention and FIGS. 2a and 2b together show a detailed circuitarrangement. A

In FIG. 1 a a represent the code pulse inputs and p the alarm input. VlV4 are flip-flops actuated by incoming code pulsesand the actuation ofV2 V4 is accomplished via AND- gates GV2 GV4. All AND-gates feeddirectly and AND-gate GL5, which thus requires signals at all inputs forfunction. There are also a number of gates Ga Gd which are connected toan OR-circuit, which is activated and causes alarm when output signalsare obtained from anyone of the gates Ga-Gd. The inputs of gates Ga Gdare connected to the code inputs, the alarm input and to the outputs ofcertain flip-flops.

The lock is so designed that for proper function a code pulse mustarrive via cross wire field and proper push button, the gate Ga thenmaintaining rest condition. Code pulse a also switches the flip-flop V1,the gate Ga then being brought out of function and the first conditionfor lock release is met simultaneously with the preparation of gate GV2via code ulse a.

p As flip-flop V1 is in actuated condition and gate GV2 prepared thegate will pass the succeeding code pulse b to flipflop V2, which then isswitched. Code pulse b thus can inhibit the alarm pulse in the gate Gbsimultaneously with its arrival to gate GV3 then being prepared. Thefunction course is then repeated for consecutive pulses c and d.However, if a new pulse should appear at a after the receipt of pulsebalarm is released via gate Gc, wherein no neutralizing of the alarmpulse is obtained in the absence of code pulse c.

Thus, the condition for lock release is that all flip-flops Vl V4 havebeen switched in proper consecutive order. Thelock function iscontrolled by the AND-circuit GL5, which sends an output signal when allflip-flops havebeen switched and set in actuated condition.Alternatively the AND-circuit GLa is controlled only by the flip flopV4, which cannot be switched until all preceeding flip-flops in thechain have been actuated in proper order.

The flip-flops V1 V4.can be bistable and a time constant for the wholesystem is then introduced with coordinated resetting. The time constantcan suitably be regulated by the alarm pulse p.

FIGS. 2a and 2b illustrate the detailed circuitry of a preferredembodiment of the invention and FIG. 2b should be placed below FIG. 2ain order to obtain a properly combined arrangement. In order not tooverload the drawings unnecessarily with connection wires terminals areshown in both Figures, the principle being that terminals with identicalreferences are interconnected. The drawings include further a largenumber of coupling elements as resistors, capacitors and diodes, theobject of which is to give the various electronic relay circuits properpotential levels at proper times. Most of these elements constitute nopart of the invention and such 1 elements have not been referenced andwill not be specially mentioned in the following specification, whichonly refers to elements, active as well as passive, and functions beingof importance for the understanding of the invention.

FIG. 2a illustrates a cross wire field with a number of horizontal wiresand associated push button contacts 0 9, and a number of vertical wiresa d, each vertical wire being connected to a predetermined horizontalwire, for example at the marked junctions. As the lock can be releasedonly by a consecutive pulse order a,b,c,d this means that theillustrated code is 3,0,6,7. This code can of course be easily changedby selecting other junctions. The code pulses are passed via thevertical wires to the flip-flops, here represented by the transistorpairs TlT2,T3T4,T5T6,T7T8 and transistor combinationsT9T10,T11T12,T13Tl4,T15T16 in FIG. 2b representing the gates Ga Gd inFIG. 1. The feeding of these gates is made partly via terminals W1 W4and partly via terminals Y1 Y4, the latter corresponding to the alarminput p in FIG. 1. The outputs Q1 Q4 from these gates are connected totransistor T17, which represents the OR-circuit GLa in FIG. 1 causingalarm when actuated. The gate outputs are also connected to the gatesT9T10 T15Tl6 via terminals X and Z for neutralization, when necessary,of applied alarm pulses and via terminals R to the lock circuit, whichhas AND- function and here is represented by transistors T18 T20.

The previously mentioned switching of flip-flops T1T2 T7T8 will now bedescribed more in detail in connection with FIG. 2a where it should benoted that switching occurs first at the termination of the applied codepulse.

Switching of the flip-flops is obtained by the presence of a capacitor Cin the base circuit of one transistor in each pair. This capacitor ischarged by the applied code pulse and the as sociated base electrodereceives the proper potential first at discharge of said capacitor,which happens at the end of the code pulse.

Take for example .pulse a which is applied to the first code stepincluding flip-flop TlT2 and through the terminal W1 to gate T9T10thereby short-circuiting the base of transistor T9 to ground andinhibiting the alarm (alarm pulse arrives simultaneously via terminalY1). Pulse a actuates the first flip-flop T1T2 so that transistor T1 ismade conducting at discharge of capacitor C resulting in a pulse atterminal XlZ2 and this condition is then maintained which meansinhibiting function at gate T9Tl0, i.e. transistor T9 short-circuits thebase of transistor T10 thus preventing output signal at the Q1 output ofthe gate. Output signals at terminals 0 are always negative intheselected example.

At arrival of code pulse a the base of transistor T1 goes negative thusmaking Tl conducting and as a result thereof also making T2 conducting.A special potential condition is then established by aid of resistors rwhich constitute a potential divider andcorrespond to the AND-gates GV2GV4 in FIG. 1. This established potential condition makes then theproper function possible at arrival of the next code pulse b.

When code pulse b is applied to next. flip-flop the condition thereofwill be influenced first at the termination of the pulse when adischarge occurs via the lower resistor r and transistor tial onterminals Q1 O4 is obtained when one or more of transistors Tl0,T12, T14or T16 are made conducting and this happens only in connection withimproper handling of the lock, i.e. wrong order between the input codepulses.

lclaim: 1. An electronic code lock device comprising: lock release meanscomprising a plurality of multi-stable serially connected elements eachelement having a parallel input and a parallel output, said lock releasemeans only being responsive to the application of code pulses to saidparallel input in a predetermined sequential manner to generate a signalon each of the parallel outputs, each signal defining the state of arespective multi-state element, and said plurality of signals defining alock release signal; and alarm actuating means having a plurality ofparallel monitoring inputs each respectively coupled to said paralleloutputs of each multi-stable element and sensing the state thereof, saidalarm actuating means generating an alarm signal only in response tostates of said multi-state elements indicative of the application ofcode pulses to said multi-stable element parallel inputs in a mannerother than in said predetermined manner.

2. The device of claim 1, further including a lock release mechanism,said lock release mechanism being coupled to each of said paralleloutputs of said multi-stable element, said lock release mechanism beingresponsive to said lock release signal.

3. The device of claim 1, wherein said alarm actuating means includes aplurality of sampling gates having inputs coupled to selected paralleloutputs of said multi-stable elements, each sampling gate further beingcoupled to a common alarm interrogation input, the coexistence at anysampling gate of an alarm interrogation signal and a state of amulti-stable element parallel output indicative of code pulseapplication in a manner other than in said predetermined mannereffecting actuation of said sampling gate and generation of said alarmsignal.

April 11, 1972 Patent No 3 656 11-14 I Dated Tore Gottfrid HesselgrenInventor(s) It is certified that error appears in the above-identifiedpatent and that said Letters Patent are hereby corrected as shown below:

In the grant (only) insert the attached sheet:

Signed and sealed this 6th day of March 1973.

(SEAL) Attest;

EDWARD MJ LIYICIIER ,.IR. ROBERT GOTTSCHALK Attest'ing OfficerCommissioner of Patents FORM PC1-1050 (10-69 USCOMM-DC 60315-1 69 i U SvGOVERNMENT PRINYING OFFICE (969 0-365-334.

1. An electronic code lock device comprising: lock release meanscomprising a plurality of multi-stable serially connected elements eachelement having a parallel input and a parallel output, said lock releasemeans only being responsive to the application of code pulses to saidparallel input in a predetermined sequential manner to generate a signalon each of the parallel outputs, each signal defining the state of arespective multi-state element, and said plurality of signals defining alock release signal; and alarm actuating means having a plurality ofparallel monitoring inputs each respectively coupled to said paralleloutputs of each multi-stable element and sensing the state thereof, saidalarm actuating means generating an alarm signal only in response tostates of said multi-state elements indicative of the application ofcode pulses to said multi-stable element parallel inputs in a mannerother than in said predetermined manner.
 2. The device of claim 1,further including a lock release mechanism, said lock release mechanismbeing coupled to each of said parallel outputs of said multi-stableelement, said lock release mechanism being responsive to said lockrelease signal.
 3. The device of claim 1, wherein said alarm actuatingmeans includes a plurality of sampling gates having inputs coupled toselected parallel outputs of said multi-stable elements, each samplinggate further being coupled to a common alarm interrogation input, thecoexistence at any sampling gate of an alarm interrogation signal and astate of a multi-stable element parallel output indicative of code pulseapplication in a manner other than in said predetermined mannereffecting actuation of said sampling gate and generation of said alarmsignal.